Description: The Artship Technology Inc. 24LC16B (24XX16*) is a Kbit Electrically Erasable PROM. The device is organized as eight blocks of X 8- bit. serial interface. Low voltage design permits operation down to volts with standby and active currents of only 5 µA and 1 mA respectively. The 24LC16B also. 24LC16B Datasheet, 24LC16 2kx8(16k) Serial CMOS EEPROM Datasheet, buy 24LC
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But I could successfully verify that the chips decode the status of the address pins. A while ago, I have developed a system similar to this with up to 5 SXes on one bus.
24LC16B Datasheet catalog
In the end, this solution my be even cheaper as one 24LC64 replaces four 24LC16 chips, and there is no need for some “tricky” decoding. Nate, I was just curious, and got the ST datasheet for their 24C So that means, not only is it limited to only one of those devices, but only one of any device, right?
Sign In or Register to comment. Perhaps datasehet consider using 24LC64 chips instead. So it would be getting all of the bytes sent to it also.
Hey, you can find the datasheet for the 24LC16 here: Maybe, this explains the difference. Quick Links Categories Recent Discussions. Seems as if there actually can only be one 24LC16 on a bus without additional decoding.
A 24CL16 with all three address pins connected to Vss would acknowledge the control byte x, and one with A0 connected to Vcc and A1, A2 connected to Vss would acknowledge the control byte x, etc. They definitely allow for eight devices on a bus, and they have two datasyeet bytes following the control byte in order to address the full range of the memory.
Addressing of the devices is performed by sending a control byte via the bus. This doesn’t mean that you couldn’t use more than 1 chip, simply that you cannot use the multiple IC2 address protocall. I use the 24LC64 in some of my SX applications with no problems.
24LC16B-I/SN Microchip | Ciiva
Thanks for your help! Gunther, Page 11 of said datasheet states that A0, A1, and A2 are not connected in this device. Nate Post Edited Nate: Their 01 and 02 devices actually have the three address bits decoded, the 04 device has two bits decoded, the 08 device just one, and the 16 device none at all.
In these datasheets they also state that the address pins are not datasheer.
In this system, each of the SXes could act as master and slave, therefore I also had to handle bus arbitration but it worked nicely in the end. Let’s say I have an sx set up as a slave on that same bus, and i would like to send some info to only the sx, I could set the address to some 224lc16b number, but the eeprom would answer to any address, correct?
Nate, this is strange.
I am looking to have possible 4 sx’s set up as slaves, and 1 eeprom and one rtc all set up on the same i2c bus if thats possible. Comments 9 Comments sorted by Date Added Votes. Where none of the Micochip equivalents do address decoding at all.
I did not use the 24LC16 so far but “smaller” devices, like the 24LC I realise that i could probably set the write protect pin of the eeprom, but i would rather just get a different chip. As the address following the control byte is only 8 bits wide, three additional bits are required to cover the 24lc1b address space of bytes. On the other hand, on page 6 where the control byte is explained, they say that the three eatasheet in the control byte are used to select one of the eight word blocks of the memory.
John, fortunately, this is not the case.